1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a manufacturing method of an oxide semiconductor thin-film transistor (TFT) substrate and a structure thereof.
2. The Related Arts
Flat panel display devices have a variety of advantages, such as thin device body, low power consumption, and being free of radiation, and are thus of wide applications. The flat panel display devices that are currently available generally comprise liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).
A comparison between the OLED display technology that is based on organic light emitting diodes and the mature LCD reveals that the OLED is a self-luminous display device having advantages of being self-luminous, high contrast, wide view angle (reaching 170°), fast response, high luminous efficiency, low operation voltage (3-10V), and being ultra-thin (thickness being less than 2 mm) and possessing excellent color display quality, a widened viewing range, and enhanced design flexibility.
Thin-film transistors (TFTs) are a vital constituent component of the flat panel display device and can be formed on a glass substrate or a plastic substrate to serve as a switching device and a driving device in for example LCDs, OLEDs, and electrophoretic displays (EPDs).
Oxide semiconductor TFT technology is one of the hottest contemporary techniques. The oxide semiconductors have a relatively high electron mobility (the electron mobility of the oxide semiconductors being greater than 10 cm2/Vs, while the mobility of a-Si is only 0.5-0.8 cm2/Vs) and, compared to low-temperature poly-silicon (LTPS), the oxide semiconductor has a simple manufacturing process and has relatively high compatibility with a-Si manufacturing processes, making it possible to be applied to LCDs (Liquid Crystal Displays), organic light emitting displays (OLEDs), and flexible displays and also applicable to displays of both large and small sizes and having a prosperous future of development and applications so as to be the hot topic of contemporary researches of the industry.
However, the applications and developments of the oxide semiconductor still face a lot of challenges.
FIG. 1 shows a conventional BCE (Back Channel Etching) TFT, which has a simple structure and less steps of manufacture and is the one that has the highest yield rate and is the most mature in the manufactures of a-Si TFT. Thus, developing BCE oxide semiconductor TFT that has excellent performance is also a hot issue of contemporary researches. A conventional BCE oxide semiconductor TFT comprises a substrate 100, a gate terminal 200, a gate insulation layer 300, and an oxide semiconductor layer 600 located on the gate insulation layer 300. After the formation of the oxide semiconductor layer 600, metal source/drain electrodes 400 are formed. The metal electrodes uses a wet etching process in which a strong acid and the mixture (HNO3/H3PO4/CH3COOH) thereof is used, which may cause damage to the oxide semiconductor in the back channel, making the manufacture more difficult. The source/drain electrodes 400 are generally of a great thickness and it is hard to control line widths in patternization operations. It is easy to cause deviation of the channel width.
FIG. 2 shows a conventional ESL (Etch Stop Layer) TFT, which comprises a substrate 100, a gate terminal 200, a gate insulation layer 300, IGZO (Indium Gallium Zinc Oxide) formed on the gate insulation layer 300, and metal source/drain electrodes 400. The channel of IGZO 600 comprises thereon a protection layer 700 to protect the IGZO 600 from being damaged. However, an additional process of forming the ESL 700 is needed and the width of the channel is increased, making the size of the TFT expanded and the available design space reduced.
FIG. 3 shows a conventional reversed coplanar TFT, which comprises a substrate 100, a gate terminal 200, a gate insulation layer 300, source/drain electrodes 400 that are formed earlier, and IGZO 600 that is formed later. Due to the thickness of the source/drain electrodes 400, it is easy for the IGZO 600 to become poor on the side slopes of the channel, making the performance affected. Further, metal ions of source/drain electrodes 400 may easily diffuse from the cutting site thereof into the IGZO 600 so as to contaminate the IGZO 600. The source/drain electrodes 400 are generally of a great thickness and it is hard to control line widths in patternization operations. It is easy to cause deviation of the channel width.